1. Field of the Invention
The present invention relates to a conductivity modulated MOSFET which makes use of bipolar operation, and more particularly to a conductivity modulated MOSFET which does not cause latch up phenomenon and which can pass a high electric current therethrough.
2. Description of the Prior Art
There have been proposed a variety of conductivity modulated MOSFET. In this respect, a reference can be made to U.S. Pat. No. 4,072,975. In general, a conductivity modulated MOSFET composed of N-channel MOSFET has a structure depicted in FIG. 1. Its principal structure comprises a source electrode 1, a gate electrode 2, a drain electrode 3, an N.sup.- base layer 4, a P.sup.+ layer 5, a P base layer 6, a p.sup.+ drain layer 7, an N.sup.+ source layer 8, a gate polycrystalline silicon layer 9, a gate oxide film 10, and a phospho-silicate-glass (hereinafter referred to as "PSG") insulating layer 11. A source terminal S is connected to the source electrode 1, a gate terminal G is connected to the gate electrode 2, and a drain terminal D is connected to the drain electrode 3.
If a voltage not less than a predetermined threshold value is applied between the source electrode 1 and the gate electrode 2, a surface of the P base layer 6 beneath the gate polycrystalline silicon layer 9 causes inversion to form a channel for electrons, and as a result, the source and the drain are converted to conductive states. If the electrons which migrate into the N.sup.- base layer 4 through this channel reach the P.sup.+ drain layer 7, positive holes injection of the N.sup.- base layer 4 is caused. A conductivity of the N.sup.- base layer 4 is modulated according to this positive holes injection, and the conductivity is extremely increased. As a result, a high electric current can be passed through the device. One of important advantages of the device is that the electric current becomes 10 to 20 times that of the conventional vertical type power MOSFET which is not provided with any P.sup.+ drain layer 7.
The operations of the aforementioned device will hereinafter be explained with reference to FIG. 2 which illustrates an equivalent circuit of the device having the structure shown in FIG. 1. The circuit comprises, in addition to an MOSFET 31, a base shunting resistor Rp, a PNP transistor 32, and an NPN transistor 33. The PNP transistor 32 consists of the P base layer 6, the N.sup.- base layer 4, and the P.sup.+ drain layer 7 shown in FIG. 1, while the NPN transistor 33 consists of the N.sup.+ source layer 8, the P base layer 6 and the N.sup.- base layer 4. Above-mentioned "base shunting resistor Rp" means the resistance observed when the P base layer 6 and the P.sup.+ layer 5 are connected to the source electrode in series. When a voltage not less than the threshold value is applied to the gate to let the MOSFET 31 turns to on-state, and electrons derived from the source migrate into the base of the PNP transistor 32, and as a result, the device is put in on-state operation.
The conductivity modulated vertical MOSFET exhibits an advantage such that the device makes it possible to pass a large electric current therethrough. However, as will be apparent from FIG. 2, it suffers from a disadvantage such that the device accompanies a latch up phenomenon derived from a parasitic thyristor formed by the NPN transistor 33 and the PNP transistor 32. In other words, since a voltage drop access the base shunting resistor Rp is small in the region the electric current between the source and drain is low, only a limited strength of electric current can pass through the NPN transistor 33, and thus the electric current can pass through only the PNP transistor 32. As the gate voltage applied to the MOSFET 31 is increased, the voltage drop across the base shunting resistor Rp increases, and finally the parasitic thyristor becomes on-state. At this stage, the electric current is spontaneously latched by the parasitic thyristor portion without supplying the gate voltage for the MOSFET 31. Therefore, the main electric current cannot be shut-off. This state is referred to as "latch up phenomenon", and the maximum value of electric current to be passed through a vertical MOSFET is limited due to the latch up phenomenon.
The latch up phenomenon is likely to occur during turn off immediately after shutting off the gate voltage. In other words, the electrons flowing from the MOSFET 31 to the base of the MOSFET 32 are suddenly stopped when the MOSFET 31 shown in FIG. 2 is in off-state. Thus, electrons which are recombined within the base run out, and as a result, a large amount of positive holes migrate through the base shunting resistor Rp without recombination with electrons. For this reason, the parasitic thyristor is likely to operate.
Upon switching off the conductivity modulated MOSFET or during the turn off state thereof, the latch up phenomenon is easily caused, which makes it difficult to shorten the turn off time. This is a severe disadvantage of the conductivity modulated MOSFET encountered when the device is used as a switching device.